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EL1508
Data Sheet March 26, 2007 FN7014.5
Differential DSL Line Driver
The EL1508 is designed for driving full rate ADSL signals in both CO and CPE applications at very low power dissipation. The high drive capability of 450mA makes this driver ideal for both CAP and DMT designs. It contains two wideband, high-voltage, current mode feedback amplifiers with a number of power dissipation reduction features. These drivers achieve an MTPR distortion measurement of better than 70dB, while consuming typically 6mA of total supply current. This supply current can be set using a resistor on the IADJ pin. Two other pins (C0 and C1) can also be used to adjust supply current to one of four pre-set modes (full-IS, 2/3-IS, 1/3-IS, and full power-down). The EL1508 operates on 5V to 12V supplies and retains its bandwidth and linearity over the complete supply range. The device is supplied in a thermally-enhanced 20 Ld SOIC (0.300"), a thermally-enhanced 16 Ld SOIC (0.150"), and the small footprint (4x5mm) 24 Ld QFN packages. The EL1508 is specified for operation over the full -40C to +85C temperature range.
Features
* 450mA output drive capability * 43.6VP-P differential output drive into 100 * 2nd/3rd harmonics of -85dBc/-75dBc * MTPR of -70dB * Operates down to 3mA per amplifier supply current * Power control features * Pin-compatible with EL1503 * Pb-free plus anneal available (RoHS compliant)
Applications
* ADSL line driver * HDSL line driver * Video distribution amplifier * Video twisted-pair line driver
Pinouts
EL1508 [20 LD SOIC (0.300")] TOP VIEW
VIN-A 1 VOUTA 2 VS- 3 GND* 4 GND* 5 GND* 6 GND* 7 VIN+A 8 C1 9 C0 10 POWER CONTROL LOGIC +-+ A B 20 VIN-B 19 VOUTB 18 VS+ 17 GND* 16 GND* 15 GND* 14 GND* 13 VIN+B 12 IADJ 11 NC
EL1508 [16 LD SOIC (0.150")] TOP VIEW
24 VOUTA VIN-A 1 VOUTA 2 VS- 3 GND* 4 GND* 5 VIN+A 6 C1 7 C0 8 POWER CONTROL LOGIC +-+ 16 VIN-B 15 VOUTB 14 VS+ 13 GND* 12 GND* 11 VIN+B 10 IADJ NC 6 9 NC GND 7 NC 1 NC 2 VS- 3 NC 4 NC 5
EL1508 (24 LD QFN) TOP VIEW
20 VOUTB 19 NC 18 NC 17 VS+ THERMAL PAD 16 NC 15 NC 14 NC 13 GND C0 10 VIN+B 12 VIN+A 8 IADJ 11 C1 9 23 VIN-A 21 VIN-B
*GND PINS ARE HEAT SPREADERS
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2001-2005, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
22 NC
EL1508 Ordering Information
PART NUMBER EL1508CS EL1508CS-T7 EL1508CS-T13 EL1508CSZ (See Note) EL1508CSZ-T7 (See Note) EL1508CSZ-T13 (See Note) EL1508CM EL1508CM-T13 EL1508CMZ (See Note) EL1508CMZ-T13 (See Note) EL1508CL EL1508CL-T7 EL1508CL-T13 EL1508CLZ (See Note) EL1508CLZ-T7 (See Note) EL1508CLZ-T13 (See Note) PART MARKING EL1508CS EL1508CS EL1508CS EL1508CSZ EL1508CSZ EL1508CSZ EL1508CM EL1508CM EL1508CMZ EL1508CMZ 1508CL 1508CL 1508CL 1508CLZ 1508CLZ 1508CLZ TAPE & REEL 7" 13" 7" 13" 13" 13" 7" 13" 7" 13" PACKAGE 16 Ld SOIC (0.150") 16 Ld SOIC (0.150") 16 Ld SOIC (0.150") 16 Ld SOIC (0.150") (Pb-Free) 16 Ld SOIC (0.150") (Pb-Free) 16 Ld SOIC (0.150") (Pb-Free) 20 Ld SOIC (0.300") 20 Ld SOIC (0.300") 20 Ld SOIC (0.300") (Pb-Free) 20 Ld SOIC (0.300") (Pb-Free) 24 Ld QFN 24 Ld QFN 24 Ld QFN 24 Ld QFN (Pb-Free) 24 Ld QFN (Pb-Free) 24 Ld QFN (Pb-Free) PKG. DWG. # MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0046 MDP0046 MDP0046 MDP0046 MDP0046 MDP0046
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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FN7014.5 March 26, 2007
EL1508
Absolute Maximum Ratings (TA = 25C)
VS+ to VS- Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . -0.3V to 28V VS+ Voltage to Ground . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 28V VS- Voltage to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . -28V to 0.3V Driver VIN+ Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS- to VS+ C0, C1 Voltage to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V IADJ Voltage to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 4V Current into any Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8mA Output Current from Driver (Static) . . . . . . . . . . . . . . . . . . . . 100mA Operating Temperature Range . . . . . . . . . . . . . . . . .-40C to +85C Storage Temperature Range . . . . . . . . . . . . . . . . . .-60C to +150C Operating Junction Temperature . . . . . . . . . . . . . . .-40C to +150C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER SUPPLY CHARACTERISTICS IS+ (Full IS) IS- (Full IS) IS+ (2/3 IS) IS- (2/3 IS) IS+ (1/3 IS) IS- (1/3 IS) IS+ (6.8k) IS- (6.8k) IS+ (Power-down) IS- (Power-down) IGND
VS = 12V, RF = 2.2k, RL= 65, IADJL = C0 = C1 = 0V, TA = 25C. Amplifiers tested separately. DESCRIPTION CONDITIONS MIN TYP MAX UNIT
Positive Supply Current per Amplifier Negative Supply Current per Amplifier Positive Supply Current per Amplifier Negative Supply Current per Amplifier Positive Supply Current per Amplifier Negative Supply Current per Amplifier Positive Supply Current per Amplifier Negative Supply Current per Amplifier Positive Supply Current per Amplifier Negative Supply Current per Amplifier GND Supply Current per Amplifier
All outputs at 0V, C0 = C1 = 0V All outputs at 0V, C0 = C1 = 0V All outputs at 0V, C0 = 5V, C1 = 0V All outputs at 0V, C0 = 5V, C1 = 0V All outputs at 0V, C0 = 0V, C1 = 5V All outputs at 0V, C0 = 0V, C1 = 5V All outputs at 0V, C0 = C1 = 0V, RADJ = 6.8k All outputs at 0V, C0 = C1 = 0V, RADJ = 6.8k All outputs at 0V, C0 = C1 = 5V All outputs at 0V, C0 = C1 = 5V All outputs at 0V
10 -9.5 7 -6 3.75 -2.75 3 -3.75 0.75 0
14.5 -13.5 10 -9 5.25 -4.25 3.75 -2.9 1.2 -0.25 1
18 -17.5 12.5 -12 7 -6 4.5 -2.25 2 -2
mA mA mA mA mA mA mA mA mA mA mA
INPUT CHARACTERISTICS VOS VOS IB+ IBIBROL eN iN VIH VIL IIH1 IIH0 IIL Input Offset Voltage VOS Mismatch Non-Inverting Input Bias Current Inverting Input Bias Current IB- Mismatch Transimpedance Input Noise Voltage -Input Noise Current Input High Voltage Input Low Voltage Input High Current for C1 Input High Current for C0 Input Low Current for C0 or C1 C0 and C1 inputs C0 and C1 inputs C1 = 5V C0 = 5V C0 = 0V, C1 = 0V 1 0.5 -1 2 1 2.25 0.8 6 3 1 -10 -5 -15 -50 -25 1.1 0 2.9 3.5 13 1 0 10 5 15 50 25 5 mV mV A A A M nV/ Hz pA/ Hz V V A A A
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FN7014.5 March 26, 2007
EL1508
Electrical Specifications
PARAMETER OUTPUT CHARACTERISTICS VOUT Loaded Output Swing RL = 100 RL = 25 IOL IOUT Linear Output Current Output Current AV = 5, RL = 10, f = 100kHz, THD = -60dBc VOUT = 1V, RL = 1 10.6 9.8 10.8 10.2 450 1 11.5 10.6 V V mA A VS = 12V, RF = 2.2k, RL= 65, IADJL = C0 = C1 = 0V, TA = 25C. Amplifiers tested separately. (Continued) DESCRIPTION CONDITIONS MIN TYP MAX UNIT
DYNAMIC PERFORMANCE BW HD2 -3 dB Bandwidth 2nd Harmonic Distortion AV = +5 fC = 1MHz, RL = 100, VOUT = 2VP-P fC = 1MHz, RL = 25, VOUT = 2VP-P HD3 3rd Harmonic Distortion fC = 1MHz, RL = 100, VOUT = 2VP-P fC = 1MHz, RL = 25, VOUT = 2VP-P MTPR SR Multi-Tone Power Ratio Slewrate 26kHz to 1.1MHz, RLINE = 100, PLINE = 20.4dBM VOUT from -8V to +8V measured at 4V 450 80 -90 -80 -90 -75 -70 600 800 MHz dBc dBc dBc dBc dBc V/s
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FN7014.5 March 26, 2007
EL1508 Pin Descriptions
16 Ld SOIC (0.150") 1 20 Ld SOIC (0.300") 1 24 Ld QFN 23 PIN NAME VIN-A FUNCTION Channel A Inverting Input CIRCUIT
CIRCUIT 1 2 3 4, 5 6 2 3 4, 5, 6, 7 8 24 3 7 8 VOUTA VSGND VIN+A Channel A Output Negative Supply Ground Connection Channel A Non-inverting Input
VS+
(Reference Circuit 1)
VS-
CIRCUIT 2 7 9 9 C1 Current Control Bit 1
VS+
6.7V
CIRCUIT 3 8 9 10 10 11 12 10 1, 2, 4, 5, 6, 14, 15, 16, 18, 19, 22 11 C0 NC IADJ Current Control Bit 2 Not Connected Supply Current Control Pin
VS+
(Reference Circuit 3)
IADJ
GND
CIRCUIT 4 11 12, 13 14 15 16 13 14, 15, 16, 17 18 19 20 12 13 17 20 21 VIN+B GND VS+ VOUTB VIN-B Channel B Non-inverting Input Ground Connection Positive Supply Channel B Output Channel B Inverting Input (Reference Circuit 1) (Reference Circuit 1) (Reference Circuit 2)
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FN7014.5 March 26, 2007
EL1508 Typical Performance Curves
24 22 GAIN (dB) 20 RF=3k 18 16 14 100K AV=10 VS=12V RL=100 RADJ=0 18 RF=2k RF=2.5k GAIN (dB) RF=1.5k 16 14 RF=4k 12 10 8 100K RF=3.5k AV=5 VS=12V RL=100 RF=3k RF=2k
RF=2.5k
1M
10M FREQUENCY (Hz)
100M
1M
10M
100M
FREQUENCY (Hz)
FIGURE 1. DIFFERENTIAL FREQUENCY RESPONSE vs RF (1/3 POWER MODE)
24 22 GAIN (dB) 20 18 16 14 100K RF=3k RF=2.5k
FIGURE 2. DIFFERENTIAL FREQUENCY RESPONSE (1/3 POWER MODE)
18 16
AV=10 VS=12V RL=100 RADJ=0
AV=5 VS=12V RL=100 RF=4k RF=2k RF=2.5k RF=3k
RF=2k
RF=1.5k GAIN (dB) 14 RF=3.5k 12 10 8 100K
1M
10M
100M
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 3. DIFFERENTIAL FREQUENCY RESPONSE vs RF (2/3 POWER MODE)
24 22 GAIN (dB) 20 RF=2k 18 16 14 100K RF=2.5k RF=3k
FIGURE 4. DIFFERENTIAL FREQUENCY RESPONSE (2/3 POWER MODE)
18 16
AV=10 VS=12V RL=100 RADJ=0
AV=5 VS=12V RL=100 RF=4k
RF=1.5k GAIN (dB) 14 RF=3k 12 RF=3.5k 10 8 100K
RF=2k RF=2.5k
1M
10M
100M
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 5. DIFFERENTIAL FREQUENCY RESPONSE vs RF (FULL POWER MODE)
FIGURE 6. DIFFERENTIAL FREQUENCY RESPONSE (FULL POWER MODE)
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FN7014.5 March 26, 2007
EL1508 Typical Performance Curves
26 22 MAGNITUDE (dB) 18 50pF 14 22pF 10 6 10K 0pF VS=12V RFB=3k AV=5 RL=83 RSET=0
(Continued)
26
100pF 68pF MAGNITUDE (dB)
VS=12V RFB=3k 22 AV=5 RL=83 RSET=0 18 14
150pF 100pF 62pF
39pF 10 6 10K 22pF 0pF
100K
1M FREQUENCY (Hz)
10M
100M
100K
1M FREQUENCY (Hz)
10M
100M
FIGURE 7. EL1508CM SINGLE-ENDED CONFIGURATION FREQUENCY RESPONSE vs CL (1/3 POWER MODE)
26 22 MAGNITUDE (dB) 18 14 39pF 10 6 10K 22pF 5pF 100K 1M FREQUENCY (Hz) 10M 100M
FIGURE 8. EL1508CM SINGLE-ENDED CONFIGURATION FREQUENCY RESPONSE vs CL (1/3 POWER MODE)
6 5
100pF 62pF
PEAKING (dB)
VS=12V RFB=3k AV=5 RL=83 RSET=0
150pF 4 3 2 1 0
VS=12V RFB=3k AV=10 RL=100
5
6
7
8
9
10
TOTAL IS (mA)
FIGURE 9. EL1508CM SINGLE-ENDED CONFIGURATION FREQUENCY RESPONSE vs CL
6 5 PEAKING (dB) 4 3 2 1 0 7 6 PEAKING (dB) 5 4 3 2 1 0
FIGURE 10. PEAKING vs IS+
VS=12V RFB=3k AV=10 RL=100
VS=7.5V RFB=3k AV=10 RL=100
0
2
4
6
8
10
5
7
9
11
13
15
RADJ (k)
ISUPPLY (mA)
FIGURE 11. PEAKING vs RADJ
FIGURE 12. PEAKING vs IS+
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FN7014.5 March 26, 2007
EL1508 Typical Performance Curves
40 -20 30 20 10 -80 0 10K 100K 1M FREQUENCY (Hz) 10M 100M -100 10K 100K 1M FREQUENCY (Hz) 10M 100M GAIN (dB) ROUT () -40 -60 A to B B to A
(Continued)
0
FIGURE 13. OUTPUT IMPEDANCE
100 VOLTAGE NOISE (nV/Hz), CURRENT NOISE (pA/Hz) 1.4 1.2 1.0 0.8 0.6 0.4 0.2
FIGURE 14. CHANNEL SEPARATION
DIFFERENTIAL GAIN (%), PHASE ()
VS=12V RFB=3k AV=2 RSET=0
DIFF GAIN
CURRENT NOISE 10 VOLTAGE NOISE
DIFF PHASE
1 10
100
1K FREQUENCY (Hz)
10K
100K
0 1.0
1.5
2.0
2.5
3.0
3.5
4.0
NUMBER of 150 RESISTOR LOADS
FIGURE 15. VOLTAGE AND CURRENT NOISE vs FREQUENCY
FIGURE 16. DIFFERENTIAL GAIN/PHASE, FO=3.58MHz (2/3 POWER MODE)
0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 1 2 3 4 5 DIFF GAIN
DIFFERENTIAL GAIN (%), PHASE ()
0.25 0.20 0.15 0.10
VS=12V RFB=3k AV=2 RSET=0
DIFFERENTIAL GAIN (%), PHASE ()
0.30
DIFF GAIN
VS=12V RFB=3k AV=2 RSET=0
DIFF PHASE
DIFF PHASE 0.05 0 1.0
1.5
2.0
2.5
3.0
3.5
4.0
NUMBER of 150 RESISTOR LOADS
NUMBER of 150 RESISTOR LOADS
FIGURE 17. DIFFERENTIAL GAIN/PHASE, FO=3.58MHz (2/3 POWER MODE)
FIGURE 18. DIFFERENTIAL GAIN/PHASE, FO=3.58MHz (FULL POWER MODE)
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FN7014.5 March 26, 2007
EL1508 Typical Performance Curves - 24 Ld QFN Package
-10 FREQ=1MHz VS=5V RSET=0 RL=100 GAIN=10 HD3 0 HARMONIC DISTORTION (dB) -20 -40 -60 -80 -100 HD3 FREQ=1MHz VS=12V RSET=0 RL=100 GAIN=10
HARMONIC DISTORTION (dB)
-30
-50
-70
HD2
HD2
-90
0
1
2
3
4
5
6
7
8
9
0
5
10
15
20
25
VOUTP-P (V)
VOUTP-P (V)
FIGURE 19. HARMONIC DISTORTION TEST (1/3 POWER MODE)
0
FIGURE 20. HARMONIC DISTORTION TEST (1/3 POWER MODE)
0 HARMONIC DISTORTION (dB)
-10 -20 -30 HD (dB) -40 -50 -60 -70 -80 -90 0
FREQ=1MHz VS=5V RSET=0 RL=100 GAIN=10
-20 -40 -60 -80
HD3
FREQ=1MHz VS=12V RSET=0 RL=100 GAIN=10
HD3
HD2
HD2 -100 0 5 10 15 20 25
1
2
3
4
5
6
7
8
9
VOUTp-p (V)
VOUTP-P (V)
FIGURE 21. HARMONIC DISTORTION TEST (2/3 POWER MODE)
0 HARMONIC DISTORTION (dB)
FIGURE 22. HARMONIC DISTORTION TEST (2/3 POWER MODE)
0 HARMONIC DISTORTION (dB)
-10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0
FREQ=1MHz VS=5V RSET=0 RL=100 GAIN=10
-20 -40 -60 -80
HD3
FREQ=1MHz VS=12V RSET=0 RL=100 GAIN=10 HD3
HD2 1 2 3 4 5 6 7 8 9
HD2 -100 0 5 10 15 20 25
VOUTp-p (V)
VOUTP-P (V)
FIGURE 23. HARMONIC DISTORTION TEST (FULL POWER MODE)
FIGURE 24. HARMONIC DISTORTION TEST (FULL POWER MODE)
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FN7014.5 March 26, 2007
EL1508 Typical Performance Curves - 20 Ld SOIC (0.300") Package
0 HARMONIC DISTORTION (dB) HARMONIC DISTORTION (dB) FREQ=1MHz VS=5V RSET=0 RL=100 GAIN=10 -10 FREQ=1MHz VS=12V RSET=0 RL=100 GAIN=10
-20
-30
-40
-50
HD 2
-60 HD3 -80 0 1 2
HD2
-70 HD 3 -90 0 5 10 15 20 25
3
4
5
6
7
8
9
VOUTP-P (V)
VOUTP-P (V)
FIGURE 25. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE (1/3 POWER MODE)
FIGURE 26. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE (1/3 POWER MODE)
HARMONIC DISTORTION (dB)
HARMONIC DISTORTION (dB)
-10
-30
FREQ=1MHz VS=5V RSET=0 RL=100 GAIN=10
-10
-30
FREQ=1MHz VS=12V RSET=0 RL=100 GAIN=10
-50 HD2 -70 HD3 -90 0 1 2 3 4 5 6 7 8 9
-50
HD 2
-70 HD 3 -90
0
5
10
15
20
25
VOUTP-P (V)
VOUTP-P (V)
FIGURE 27. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE (2/3 POWER MODE)
0 HARMONIC DISTORTION (dB) -20 -40 -60 -80 HD3 -100 0 1 2 3 4 5 6 7 8
FIGURE 28. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE (2/3 POWER MODE)
HARMONIC DISTORTION (dB)
FREQ=1MHz VS=5V RSET=0 RL=100 GAIN=10
-10
-30
FREQ=1MHz VS=12V RSET=0 RL=100 GAIN=10
-50
HD 2
HD2
-70 HD 3 -90 0 5 10 15 20 25
VOUTP-P (V)
VOUTP-P (V)
FIGURE 29. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE (FULL POWER MODE)
FIGURE 30. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE (FULL POWER MODE)
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FN7014.5 March 26, 2007
EL1508 Typical Performance Curves
FREQ=1MHz VS=5V RSET=6.81k RL=100 GAIN=10 -10 FREQ=1MHz VS=5V RSET=6.81k RL=100 GAIN=10
HARMONIC DISTORTION (dB)
-10
HARMONIC DISTORTION (dB)
-30
-30
HD3
-50
HD 3 -50 HD 2 -70
-70 HD2 -90 0 1 2 3 4 5 6 7 8 9
0
1
2
3
4
5
6
7
8
9
VOUTP-P (V)
VOUTP-P (V)
FIGURE 31. EL1508CM HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE (FULL POWER MODE)
0 HARMONIC DISTORTION (dB)
FIGURE 32. EL1508CL HARMONIC DISTORTION TEST (FULL POWER MODE)
HARMONIC DISTORTION (dB)
-20
FREQ=1MHz VS=12V RSET=6.81k RL=100 GAIN=10
0 -20 -40 -60 HD2 -80 -100 FREQ=1MHz VS=12V RSET=6.81k RL=100 GAIN=10
HD3
-40
HD 2
-60 HD 3 -80 0 5 10 15 20 25
0
5
10
15
20
25
VOUTP-P (V)
VOUTP-P (V)
FIGURE 33. EL1508CM HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT VOLTAGE (FULL POWER MODE)
FIGURE 34. EL1508CL HARMONIC DISTORTION TEST (FULL POWER MODE)
VOUT
VOUT C0, C1
C0, C1 40ns/DIV
2V/DIV 40ns/DIV
2V/DIV
FIGURE 35. DISABLE TIME
FIGURE 36. ENABLE TIME
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FN7014.5 March 26, 2007
EL1508 Typical Performance Curves
21.6 OUTPUT VOLTAGE P-P (V) 21.4 21.2 21.0 20.8 20.6 50 FREQ=100kHz VS=12V RSET=0 AV=10 70 90 110 130 150 170 190
(Continued)
25 21 17 13 9 5 VS=12V RFB=10 AV=10 RL=100
IS+ (mA)
0
2
4
6
8
10
DIFFERENTIAL LOAD RESISTANCE ()
RADJ (k)
FIGURE 37. LOAD RESISTANCE vs OUTPUT VOLTAGE (ALL POWER MODES)
30 POWER DISSIPATION (W) 25 20 15 10 5 0
2/3 POW ER
OWE R
FIGURE 38. IS+ vs RADJ (FULL POWER MODE)
4.5
FU LL P
SUPPLY CURRENT (mA)
+ + + -
4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5
JA = 30C/W
JA = 43C/W JA = 53C/W JA = 80C/W
1/3 POWER
0
2
4
6
8
10
12
0 -40
-20
SUPPLY VOLTAGE (V)
20 40 60 80 0 AMBIENT TEMPERATURE (C)
100
FIGURE 39. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 40. POWER DISSIPATION vs AMBIENT TEMPERATURE for VARIOUS MOUNTED JAs (See Thermal Resistance Curve on page 15)
USING JEDEC JESD51-3 HIGH EFFECTIVE THERMAL CONDUCTIVITY. (4-LAYER) TEST BOARD, QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5
4 3.5 POWER DISSIPATION (W)
USING ELANTEC EL1503CS DEMO BOARD, 2"X2" (4-LAYER). DEMO BOARD WITH HEATSINK VIA INTERNAL GROUND PLANE
4.0 3.5 POWER DISSIPATION (W)
3 2.5 2 1.5 1 0.5 0 -40
J
A =4
3.0 3.378W 2.5 2.0 1.5 1.0 0.5 0
JA =
37
7
C/ W
C /W
-20
0
20
40
60
80
100
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (C)
AMBIENT TEMPERATURE (C)
FIGURE 41. 16 LD SOIC POWER DISSIPATION and THERMAL RESISTANCE
FIGURE 42. 24 LD QFN POWER DISSIPATION vs AMBIENT TEMPERATURE
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FN7014.5 March 26, 2007
EL1508 Applications Information
The EL1508 consists of two high-power line driver amplifiers that can be connected for full duplex differential line transmission. The amplifiers are designed to be used with signals up to 4MHz and produce low distortion levels. The EL1508 has been optimized as a line driver for ADSL CO application. The driver output stage has been sized to provide full ADSL CO power level of 20dBM onto the telephone lines. Realizing that the actual peak output voltages and currents vary with the line transformer turns ratio, the EL1508 is designed to support 450mA of output current which exceeds the level required for 1:2 transformer ratio. A typical ADSL interface circuit is shown in Figure 43 below. Each amplifier has identical positive gain connections, and optimum common-mode rejection occurs. Further, DC input errors are duplicated and create commonmode rather than differential line errors.
DRIVER INPUT+ + ROUT RF ZLINE RF + RF + RECEIVE AMPLIFIERS + RF R RIN ROUT LINE LINE +
the average output current, IO, or 1/2 IQ, whichever is the lowest. We'll call this term IX. Therefore, we can determine a quiescent current with the equation:
P Dquiescent = V S x ( I S - 21 X )
where: VS is the supply voltage (VS+ to VS-) IS is the operating supply current (IS+ - IS-) / 2 IX is the lesser of IO or 1/2 IQ The dissipation in the output stage has two main contributors. Firstly, we have the average voltage drop across the output transistor and secondly, the average output current. For minimal power dissipation, the user should select the supply voltage and the line transformer ratio accordingly. The supply voltage should be kept as low as possible, while the transformer ratio should be selected so that the peak voltage required from the EL1508 is close to the maximum available output swing. There is a trade off, however, with the selection of transformer ratio. As the ratio is increased, the receive signal available to the receivers is reduced. Once the user has selected the transformer ratio, the dissipation in the output stages can be selected with the following equation:
VS P Dtransistors = 2 x I O x ------ - V O 2
2RG
DRIVER INPUT-
RECEIVE OUT +
R RIN
where: VS is the supply voltage (VS+ to VS-) VO is the average output voltage per channel IO is the average output current per channel The overall power dissipation (PDISS) is obtained by adding PDquiescent and PDtransistor.
RECEIVE OUT -
FIGURE 43. TYPICAL LINE INTERFACE CONNECTION
Input Connections
The EL1508 amplifiers are somewhat sensitive to source impedance. In particular, they do not like being driven by inductive sources. More than 100nH of source impedance can cause ringing or even oscillations. This inductance is equivalent to about 4" of unshielded wiring, or 6" of unterminated transmission line. Normal high-frequency construction obviates any such problem.
Estimating Line Driver Power Dissipation in ADSL CO Applications
Figure 44 on the following page shows a typical ADSL CO line driver implementation. The average line power requirement for the ADSL CO application is 20dBM (100mW) into a 100 line. The average line voltage is 3.16VRMS. The ADSL DMT peak to average ratio (crest factor) of 5.3 implies peak voltage of 16.7V into the line. Using a differential drive configuration and transformer coupling with standard back termination, a transformer ratio of 1:1 is selected. With 1:1 transformer ratio, the impedance across the driver side of the transformer is 100, the average voltage is 3.16VRMA and the average current is 31.6mA. The power dissipated in the EL1508 is a
Power Supplies and Dissipation
Due to the high power drive capability of the EL1508, much attention needs to be paid to power dissipation. The power that needs to be dissipated in the EL1508 has two main contributors. The first is the quiescent current dissipation. The second is the dissipation of the output stage. The quiescent power in the EL1508 is not constant with varying outputs. In reality, 50% of the total quiescent supply current needed to power each driver is converted in to output current. Therefore, in the equation below we should subtract 13
FN7014.5 March 26, 2007
EL1508
combination of the quiescent power and the output stage power when driving the line:
Pd = P quiescent + P output-stage Pd = V S x I Q + ( V S - 2 x V OUT-RMS ) x I OUT-RMS
PCB Layout Considerations for QFN and SOIC Packages
The EL1508 die is packaged in three different thermallyefficient packages: a 20 Ld SOIC (0.300"), a 16 Ld SOIC (0.150"), and a 24 Ld QFN. The 16 Ld SOIC has the same external dimensions as a standard 0.150" width SOIC package, but has the center four leads (two per side) internally-fused for heat transfer purposes. Both packages can use PCB surface metal vias areas and internal ground planes, to spread heat away from the package. The larger the PCB area the lower the junction temperature of the device will be. In XDSL applications, multiple layer circuit boards with internal ground plane are generally used. 13 mil vias are recommended to connect the metal area under the device with the internal ground plane. Examples of the PCB layouts are shown in the figures below that result in thermal resistance JA of 37C/W for the QFN package and 47C/W for the SOIC package. The thermal resistance is obtained with the EL1508CL and CS demo boards. The demo board is a 4-layer board built with 2oz. copper and has a dimension of 4in2. Note, the user must follow the thermal layout guideline to achieve these results. In addition to lower thermal resistance, the QFN package exhibits much lower 2nd harmonic distortion. A separate Application Note for the QFN package and layout recommendations is also available.
In the full power mode and with 6.8k RADJ registers, the EL1508 consumes typically 7mA quiescent current and still able to maintain very low distortion. The distortion results are shown in typical performance section of the data sheet. When driving a load, a large portion (about 50%) of the quiescent current becomes output load current:
Pd = 12 x ( 7mA x 50% ) + ( 12V - 3.16 ) x 31.6mA x 2
where: Pd = 598mW The JA requirement needs to be calculated. This is done using the equation:
T JUNCT - T AMB JA = -------------------------------------------P DISS
where: TJUNCT is the maximum die temperature (150C) TAMB is the maximum ambient temperature (85C) PDISS is the dissipation calculated above JA is the junction to ambient thermal resistance for the package when mounted on the PCB
150 - 85 JA = --------------------- = 108C/W 598mW
TX+
+ RF
VS+ VS-
RT 10 0.22F TXFR 1:1 100
FROM AFE
2RG 1.5k TX-
3k
TOP (24 LD QFN)
+ VS+ RT 10 0.22F
VSRF 3k
FIGURE 44. TYPICAL ADSL CO LINE DRIVER IMPLEMENTATION
INTERNAL GROUND PLANE (24 LD QFN)
14
FN7014.5 March 26, 2007
EL1508
55 MOUNTED DEVICE JA (C/W) 50
Note: 2OZ COPPER USED TOP FOIL ONLY-WITH SOLDER MASK TOP FOIL-WITH 0.45in2 BOTTOM FOIL WITH MANY FEEDTHROUGHS
45 40
TOP FOIL ONLY-NO SOLDER MASK 35
30 0 2 4 6 8 10 AREA OF CIRCUIT BOARD HEAT SINK (in2)
TOP (16 Ld SO)
FIGURE 45. THERMAL RESISTANCE of 20 LD SO (0.300") EL1508 vs BOARD COPPER AREA
Power Control Function
The EL1508 contains two forms of power control operation. Two digital inputs, C0 and C1, can be used to control the supply current of the EL1508 drive amplifiers. As the supply current is reduced, the EL1508 will start to exhibit slightly higher levels of distortion and the frequency response will be limited. The 4 power modes of the EL1508 are set up as shown in the following table:
TABLE 1. POWER MODES OF THE EL1508 C1 INTERNAL GROUND PLANE (16 Ld SO) 0 0 C0 0 1 0 1 OPERATION IS full power mode 2/3 IS power mode 1/3 IS power mode Power-down
EL1508CM PCB Layout Considerations
The 20 Ld SOIC (0.300") Power Package is designed so that heat may be conducted away from the device in an efficient manner. To disperse this heat, the center four leads on either side of the package are internally fused to the mounting platform of the die. Heat flows through the leads into the circuit board copper, then spreads and convects to air. Thus, the ground plane on the component side of the board becomes the heatsink. This has proven to be a very effective technique, but several aspects of board layout should be noted. First, the heat should not be shunted to internal copper layers of the board nor backside foil, since the feedthroughs and fiberglass of the board are not very thermally conductive. To obtain the best thermal resistance of the mounted part, JA, the topside copper ground plane should have as much area as possible and be as thick as practical. If possible, the solder mask should be cut away from the EL1508 to improve thermal resistance. Finally, metal heatsinks can be placed against the board close to the part to draw heat toward the chassis. The graph below shows various JAs for the 20 Ld SOIC mounted on different copper foil areas.
1 1
Another method for controlling the power consumption of the EL1508 is to connect a resistor from the IADJ pin to ground. When the IADJ pin is grounded (the normal state), the supply current per channel is as per the specifications table on page 2. When a resistor is inserted, the supply current is scaled according to the "RSET vs IS" graphs in the Performance Curves section. Both methods of power control can be used simultaneously. In this case, positive and negative supply currents (per amp) are given by the equations below:
12.4mA I S + = 0.9mA + ------------------------------------------------------ x ( 2/3C 1 + 1/3C 0 ) ( 1 + R SET / 1574 ) 12.4mA I S - = ------------------------------------------------------ x ( 2/3C 1 + 1/3C 0 ) ( 1 + R SET / 1574 )
Output Loading
While the drive amplifiers can output in excess of 500mA transiently, the internal metallization is not designed to carry more than 100mA of steady DC current and there is no
15
FN7014.5 March 26, 2007
EL1508
current-limit mechanism. This allows safely driving rms sinusoidal currents of 2 x 100mA, or 200mA. This current is more than that required to drive line impedances to large output levels, but output short circuits cannot be tolerated. The series output resistor will usually limit currents to safe values in the event of line shorts. Driving lines with no series resistor is a serious hazard. The amplifiers are sensitive to capacitive loading. More than 25pF will cause peaking of the frequency response. The same is true of badly terminated lines connected without a series matching resistor.
Single Supply Operation
The EL1508 can also be powered from a single supply voltage. When operating in this mode, the GND pins can still be connected directly to GND. To calculate power dissipation, the equations in the previous section should be used, with VS equal to half the supply rail.
Feedback Resistor Value
The bandwidth and peaking of the amplifiers varies with supply voltage somewhat and with gain settings. The feedback resistor values can be adjusted to produce an optimal frequency response. Here is a series of resistor values that produce an optimal driver frequency response (1dB peaking) for different supply voltages and gains:
TABLE 2. OPTIMUM DRIVER FEEDBACK RESISTOR FOR VARIOUS GAINS AND SUPPLY VOLTAGES SUPPLY VOLTAGE 5V 12V DRIVER VOLTAGE GAIN 2.5 3.5k 3.5k 5 3.25k 3.25k 10 3k 3k
Output AC Coupling
When in power-down mode, several volts of differential voltage may appear across the line driver outputs. If DC current path exists between the two outputs, large DC current can flow from the positive supply rail to the negative supply rail through the outputs. To avoid DC current flow, the most effective solution is to place DC blocking capacitors in series at the outputs, as shown by the 0.22F capacitors in Figure 44.
Power Supplies
The power supplies should be well bypassed close to the EL1508. A 2.2F tantalum capacitor and a 0.1F ceramic capacitor for each supply works well. Since the load currents are differential, they should not travel through the board copper and set up ground loops that can return to amplifier inputs. Due to the class AB output stage design, these currents have heavy harmonic content. If the ground terminal of the positive and negative bypass capacitors are connected to each other directly and then returned to circuit ground, no such ground loops will occur. This scheme is employed in the layout of the EL1508 demonstration board, and documentation can be obtained from the factory.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 16
FN7014.5 March 26, 2007
EL1508 Small Outline Package Family (SO)
A D N (N/2)+1 h X 45
A E E1 PIN #1 I.D. MARK c SEE DETAIL "X"
1 B
(N/2) L1
0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X
SEATING PLANE L 4 4
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX 0.003 0.002 0.003 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. M 2/07
17
FN7014.5 March 26, 2007
EL1508 QFN (Quad Flat No-Lead) Package Family
A D N (N-1) (N-2) B
MDP0046
QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY (COMPLIANT TO JEDEC MO-220) MILLIMETERS SYMBOL QFN44 QFN3 A 0.90 0.02 0.25 0.20 7.00 5.10 7.00 5.10 0.50 0.55 44 11 11 0.90 0.02 0.25 0.20 5.00 3.80 7.00 5.80 0.50 0.40 38 7 12 QFN32 0.90 0.02 0.23 0.20 8.00 0.90 0.02 0.22 0.20 5.00 TOLERANCE 0.10 +0.03/-0.02 0.02 Reference Basic Reference Basic Reference Basic 0.05 Reference Reference Reference NOTES 8 8 4 6 5
1 2 3
A1
PIN #1 I.D. MARK E
b c D D2 E
(N/2)
5.80 3.60/2.48 8.00 6.00
2X 0.075 C
E2
2X 0.075 C
5.80 4.60/3.40 0.80 0.53 32 8 8 0.50 0.50 32 7 9
e L N ND
TOP VIEW N LEADS
0.10 M C A B (N-2) (N-1) N b
NE
L
PIN #1 I.D. 3 1 2 3
MILLIMETERS SYMBOL QFN28 QFN2 A A1 b c 0.90 0.02 0.25 0.20 4.00 2.65 5.00 3.65 0.50 0.40 28 6 8 0.90 0.02 0.25 0.20 4.00 2.80 5.00 3.80 0.50 0.40 24 5 7 QFN20 0.90 0.02 0.30 0.20 5.00 3.70 5.00 3.70 0.65 0.40 20 5 5 0.90 0.02 0.25 0.20 4.00 2.70 4.00 2.70 0.50 0.40 20 5 5 QFN16 0.90 0.02 0.33 0.20 4.00 2.40 4.00 2.40 0.65 0.60 16 4 4
TOLERANCE NOTES 0.10 +0.03/ -0.02 0.02 Reference Basic Reference Basic Reference Basic 0.05 Reference Reference Reference 4 6 5
(E2)
NE 5 (N/2)
D D2
(D2) BOTTOM VIEW
7
E E2 e L
e C SEATING PLANE 0.08 C N LEADS & EXPOSED PAD
0.10 C
N ND NE
Rev 11 2/07
SEE DETAIL "X" SIDE VIEW
NOTES: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Tiebar view shown is a non-functional feature. 3. Bottom-side pin #1 I.D. is a diepad chamfer as shown. 4. N is the total number of terminals on the device.
(c) C A
2
5. NE is the number of terminals on the "E" side of the package (or Y-direction). 6. ND is the number of terminals on the "D" side of the package (or X-direction). ND = (N/2)-NE. 7. Inward end of terminal may be square or circular in shape with radius (b/2) as shown. 8. If two values are listed, multiple exposed pad options are available. Refer to device-specific datasheet.
(L) A1 DETAIL X N LEADS
18
FN7014.5 March 26, 2007

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